The dimensions of semiconductor device features relentlessly plunge into the deep sub-micron range challenging conventional fabrication techniques. As critical dimensions shrink, it becomes increasingly more difficult to achieve high dimensional accuracy with high manufacturing throughput. The minimum feature size depends upon the chemical and optical limits of a particular lithography system, and the tolerance for distortions of the shape. In addition to the limitations of conventional lithography, the manufacturing costs attendant upon accurately forming ultrafine design features increase, thereby requiring advances in processing designed for efficient use of facilities and high manufacturing throughput.
As dimensions of feature sizes, such as lines or trenches decrease, low-k1 lithographic imaging is restrained by optical proximity effects to achieve dimensional accuracy, as by restraining low-k1 lithographic imaging to reach the diffractional limit, which is the foundational limit of a lithography system where k1=0.25. For example, when forming a line or trench, an exposure reticle 10 is formed as illustrated in FIG. 1A. However, when exposing an underlying resist layer to form the corresponding pattern, indicated by dashed line 11 (FIG. 1B), a pattern having shape 12 is formed, falling short of the desired pattern 11 due to optical proximity effects. There has evolved a method known as optical proximity correction (OPC) which basically involves repeated modification of the exposure reticle and repeated photoresist exposures until the actual pattern formed coincides with the desired design pattern. For example, in attempting to correct the undesired pattern 12 shown in FIG. 1B, a modified exposure reticle 13, shown in FIG. 1C, is formed using OPC, which modified exposure reticle 13 comprises enlarged end portions 13A and 13B. Upon photoresist exposure using modified exposure reticle 13, a pattern 14 is formed which proximates desired design pattern 11, as shown in FIG. 1D.
Double exposure techniques and spacer lithographic processes have also evolved. However, these techniques have not been completely successful and suffer from low manufacturing throughput, some techniques requiring the repeated use of several tools and frequent chemical mechanical polishing (CMP).
Accordingly, a need exists for methodology enabling the fabrication of semiconductor chips comprising devices having accurately formed features in the deep sub-micron range, such as design features less than 20 nm, including design features less than 15 nm, e.g., less than 10 nm. There exists a particular need for such methodology enabling the accurate formation of ultrafine design features with high efficiency and high manufacturing throughput.